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[Other resource] sdram_control_burst

Description: 精简的sdram读写控制器例子，适用于数据采集系统，verilog，只支持burst方式的读写-streamlined read and write SDRAM controller example, applied to the data acquisition system, Verilog. only supports burst mode read and write
Platform: | Size: 154126 | Author: 梁文锋 | Hits:

[Other resource] CommandResponse

Description: verilog语言写的sdram控制器—命令响应模块代码，经过测试，逻辑正确，可编译，可综合-verilog language written sdram controller-order response to the code, tested, logically correct, compiler, integrated
Platform: | Size: 1244 | Author: hanjian | Hits:

[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_simplifiedUI_vlog_v92

Description: verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
Platform: | Size: 908288 | Author: ma yirong | Hits:

[VHDL-FPGA-Verilog] SDRAM_controler_code

Description: SDRAM的verilog控制器代码极其仿真模块-The verilog code for SDRAM controller is extremely Simulation Module
Platform: | Size: 194560 | Author: 周仁杰 | Hits:

[VHDL-FPGA-Verilog] c_xapp260

Description: xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing Warfare and Xilinx solutions, but also explains how to use Xilinx Software tools and hardware-proven reference designs to be for your own With (from low-cost DDR SDRAM applications to such as 667 Mb/s This higher performance DDR2 SDRAM interface) design a complete deposit Storage device interface solution.
Platform: | Size: 1123328 | Author: 陈阳 | Hits:

[Other] sdr_sdram_control

Description: 一个SDRAM控制器，verilog语言设计，并在ISE上仿真实现。（内部包含多个verilog程序）-sdram-controller,use verilog langguage,it s run sucessfull
Platform: | Size: 162816 | Author: 李丽 | Hits:

[VHDL-FPGA-Verilog] verilog_sdram

Description: SDRAM读写控制的实现与Modelsim仿真,采用verilog HDL编写-sdram controller and simulate with modelsim
Platform: | Size: 2176000 | Author: bigchop ma | Hits:

[VHDL-FPGA-Verilog] controller-design-of-sdram-

Description: 基于FPGA对sdram控制器的设计（VERILOG语言）-FPGA-based controller design of sdram (VERILOG language)
Platform: | Size: 2823168 | Author: 黄飞 | Hits:

[VHDL-FPGA-Verilog] SDR_SDRAM_IP

Description: SDR SDRAM 控制器，Altera官网重要资料。内涵说明文档，和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
Platform: | Size: 2360320 | Author: peteryu010 | Hits:

[VHDL-FPGA-Verilog] 4port-sdram

Description: 4端口SDRAM控制器verilog程序-4-port SDRAM controller with verilog
Platform: | Size: 28672 | Author: xin | Hits:

[Windows Develop] DDR-SDRAM

Description: ddr sdram 控制器的源代码，内有vhdl和verilog。-DDR SDRAM controller
Platform: | Size: 903168 | Author: 何海山 | Hits:

[Other] eetop.cn_SDRAM

Description: 实现sdram控制器的verilog代码，很好的学习资料-The sdram controller verilog code, very good learning materials
Platform: | Size: 6144 | Author: 李军 | Hits:

[Other] sdr_ctrl

Description: SDRAM控制器源码 Verilog描述-SDRAM controller Verilog source description
Platform: | Size: 2054144 | Author: wang | Hits:

[VHDL-FPGA-Verilog] verilog

Description: it is xilinx SDR SDRAM controller core
Platform: | Size: 297984 | Author: roger1 | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: 用Verilog HDL语言编写的SDRAM控制器，在DE2-70的开发板上实现。-SDRAM Controller with Verilog HDL language, DE2-70 development board.
Platform: | Size: 154624 | Author: 李桐 | Hits:

[VHDL-FPGA-Verilog] Sdram_Control_4Port

Description: SDRAM控制器的verilog源代码实现-SDRAM controller Verilog source code to achieve
Platform: | Size: 3072 | Author: 麦涛涛 | Hits:

[Other] SDRAM

Description: SDRAM controller: it contains a SDRAM controller writtern in verilog language. It is a interface between microprocessor and SDRAM device.
Platform: | Size: 7168 | Author: william | Hits:

[Software Engineering] DDR3-SDRAM-controller

Description: My package named design DDR3 Synchronous Data Random Access Memory by verilog.The memory controller is a digital circuit which manages the flow of data going to and from the computer s main memory.
Platform: | Size: 6144 | Author: thuanbk | Hits:

[Embeded-SCM Develop] DDR_MO

Description: 使用verilog语言实现简单的DDR SDRAM控制器(Using Verilog language to achieve a simple DDR SDRAM controller)
Platform: | Size: 1101824 | Author: 搬砖123 | Hits:

[VHDL-FPGA-Verilog] my_sdram_mdl

Description: 此功能为altera fpga 的sdram 控制器，串口接收与发送(This feature altera fpga sdram controller, serial port to receive and send)
Platform: | Size: 1206272 | Author: flyhouse112 | Hits:
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